In processing wafers or substrates to make integrated circuits (ICs) or semiconductor devices, it is often desirable to provide a doped silicon oxide layer or film, such as a phosphosilicate glass (PSG) film. Typically, PSG films are deposited at elevated temperatures by chemical vapor deposition (CVD) through a reaction of source gases such as silane (SiH4) and phosphine (PH3) at or near the surface of the substrate. The process is carried out with plasma enhanced CVD (PECVD) in which low frequency RF (LFRF) power is coupled to the gas in the deposition chamber to form the plasma, and high frequency RF (HFRF) is applied to control the ion energies. The SiH4 and PH3 are introduced in a series of discrete steps, as shown in FIG. 1, to control the concentration of phosphorous at the beginning of deposition. FIG. 1 is a graph of the voltage applied to the mass flow controller (MFC) or metering valves over time, illustrating at least four discrete steps for increasing SiH4 and PH3 flow in a conventional process for depositing a PSG film.
In conventional processes the temperature of the substrate is raised to a final deposition temperature in a number of steps. These steps include heating the substrate to a relatively low pre-deposition temperature (340° C.) and steps in which the discrete increases in SiH4 and PH3 results in discrete increases in temperature. The final temperature is significantly higher than the pre-deposition temperature. A problem with this conventional process is that the interruption in process gas flows, i.e., SiH4 and PH3 gas flows, causes discontinuities in the film and creates interfaces rich in phosphorous or which have a relatively high percentage of phosphorous. As shown in FIG. 2, cave defects are formed along these phosphorous rich interfaces in subsequent processing. These defects were typically not a problem in previous generations of ICs, which have elements and features much larger than the size of the cave defects. However, with the shrinking geometries of the latest generation of ICs, these and other defects caused by phosphorous rich interfaces have resulted in substantially lower yields, or yield loss, in the number of working ICs or devices produced. In particular, interaction between the phosphorous rich locations and polymer formed during a self-aligned contact (SAC) etch, such as polymer formed from an etch plasma formed from CF4, and cleaning solutions, such as SC1, cause cave defects and failure of the SAC contact.
Non-uniform distribution of phosphorous through the thickness of the PSG film may result in other defects and further yield loss. FIG. 3 is a bar graph of the percent loss of lots of substrates or wafers due to one such defect, referred to as elephant's foot, which is caused by non-uniformity in the phosphorous content through a PSG film. As illustrating in FIG. 3, as much as 20 percent of wafers in a lot may be lost as a result of this defect. FIG. 4 is a graph illustrating the non-uniformity of the phosphorous content in a PSG film deposited by a conventional process.
Another problem with conventional processes for depositing a PSG film is oxidation or excess oxidation of exposed metal, such as the metal of a gate contact, due to exposure to oxygen containing gases during the CVD process. Typically, this occurs during the pre-deposition stage when the substrate is heated to the pre-deposition temperature in an oxygen containing atmosphere. For example, many conventional processes flow a mixture of helium (He) and oxygen (O2) in a 1:1 or 1.7:1 ratio while heating the substrate to the pre-deposition temperature.